Today I learned about a couple new techniques. The first one is something called "very long instruction word" (VLIW). In VLIW, a single instruction is actually composed of multiple smaller instructions which have been packed together by the compiler. The fetch and decode stages of the pipeline can effectively work with multiple instructions in parallel, but they only have to deal with a single instruction. The decode stage unpacks the sub-instructions and sends them to the appropriate functional units. The decode stage does not detect hazards and the pipeline can generally only be stalled on a cache miss, so it is the job of the compiler to insert NOP instructions (no-operation) to prevent hazards. A processor which makes use of VLIW is said to have an explicitly parallel design.
The other technique is something called an "interlock". I am still researching the specifics, but an interlock in general is some mechanism which prevents harm to either the operator or the machine (an example would be the mechanism which locks the oven door during a self-clean cycle). In the case of processors, an interlock can detect a data hazard in the decode stage of the pipeline and stall the previous stages while sending NOPs out of the decode stage until the hazard has been resolved. I am assuming that an interlock is also used to prevent one stage from passing its output to the next stage in the event that the next stage is stalled (for example, a particular instruction is taking multiple clock cycles to execute and the fetch and decode stages must be stalled).
Reposted from http://invisiblegdev.blogspot.com/
