Original Post
Hi, I don't know if this is the right place to ask, but I suppose there are some people who know a lot about electronics here. In januari I have exams so I'm obviously studying now, but we have this course about "Analog Components for Signal Processing" which handles about a lot of stuff, including Phase Lock Loops (PLLs). Now in my university a lot of professors have the bad habbit to give us no book whatsoever, only the slides they use during the classes. And slides are known to contain only a few words and no explanations whatsoever. So all I have about these PLLs is some slides with formulas and the shematic of a PLL. It never sais exactly what a PLL does tho :( If this is considered a "homework question" please close this thread. However I'm convinced that it's not, and I've been trying to find out this stuff myself too, and even google doesn't help me! Can someone help me? I have a few questions about PLL's. What does a PLL actually do? Appearantly it "locks to a frequency", but to what frequency? If it locks to the frequency of the input signal, then the output signal has the same frequency as the input signal, so why not use the input signal itself? If you use a PLL, is there actually a difference between the input and the output signal? What frequency does a PLL lock to, and for how long / until what event happens? There is also a Voltage Controlled Oscillator (VCO) in the PLL. What does this component actually do? It's output is a signal with a frequency controlled by the input, but the input itself also has some frequency already. How is the output frequency controlled? By the amplitude, the frequency of the phase of the VCO input? There is also a "lead-lag" filter in a PLL. Yet another word that pops up without any further explanation, do you know what this is and what it does? And the Phase Detector appearantly just multiplies two input signals. How can such a multiplication detect a phase? (I won't even mention the "EXOR" and "charge pump" phase detectors that appear a few slides later) And final question, it's called a PHASE lock loop, and yet all they talk about on the slides is frequencies. What's going on here? Thanks for the help and sorry for this terrible post in the GDNet Lounge, I guess it must be my exam-stress (New Year and Christmas? what's that?)