Makefile question - SOLVED

Why is it that the $@ variable is not available in the dependency list, but only in the body of the makefile block. Those are odd scoping rules, and I'm trying to get around it somehow. I'll give a simple example to show what I mean: Suppose I have something like this:

prog1: $(OBJS) prog1.o
	@echo "Linking $@..."
	@$(LD) $(LDFLAGS) -o $@ $(OBJ) $@.o

prog2: $(OBJS) prog2.o
	@echo "Linking $@..."
	@$(LD) $(LDFLAGS) -o $@ $(OBJ) $@.o

This works fine. Clearly, I'm separating the executable's linker object from the libraries' ones, since I have more than one executable. That's fine and dandy. But what if I don't want to have that ugly repeating code block? I can have a variable called DESTS, containing "prog1 prog2" and try to do something like this:

$(DESTS): $(OBJS) $@.o
	@echo "Linking $@..."
	@$(LD) $(LDFLAGS) -o $@ $(OBJ) $@.o

This works great if I don't have that $@.o in the dependency list and compile the .o separately somewhere else, but if I try to do what the sample above shows, it says it can't find ".o" (in other words, $@ is empty until the echo statement below). Am I totally on crack here? Is there a way to do this nicely? The problem with setting up .o compilation of the exe's outside of that block is that if I change just the code in (say) prog1.cpp, then it will not relink everything, because prog1.o is not in the dependency list..... help? :) [Edited by - Replicon on June 4, 2006 11:49:50 PM]