I'm trying to create a makefile where I can say something like "make foo" and the make file would take foo.cpp fooControlCommands.cpp from a subfolder called src and foo.h and fooControlCommands.cpp from a subfolder called include. The make file would then create foo.o and fooControlCommands.o and put them in a subfolder called obj then links those objects to create an executable called foo. Typing "make bar" should do the same thing except with bar.cpp and barControlCommands.cpp. I have not been able to figure out how I can setup a set of rules to do this. I hope there is a way to do this because I would prefer to not have to type out a dozen rules to do the exact same thing. Thanks for any help, jmkelm08

Its seems to me that this document describe how to do just that (Scroll down to about 40% "More about Makefiles").
I believe what they call "abstract rules" can help you out (Not quite sure though...)

If you are making a project that might grow big/huge, the rest of the document should be of interrest as well.
GNU's websites has more extensive info on these tools but their documentation is somewhat a daunting read.