17 years, 9 months ago
Highlights
Community contributions featuredNow, if not fast enough yet, have it:1) pull a whole cacheline from src1 into 4 registers.2) multiply by a whole cacheline from src2 (load execute).3) reduce (add)4) goto 1).5)…
17 years, 9 months ago
17 years, 9 months ago
In a memory bound kernel, you shouldn't be concerned by instruction pairing (hint: cachelines). You shouldn't be using msvc if you care about SSE performance either.Anyway,templ…
17 years, 9 months ago
17 years, 9 months ago
You've asked for a shift, not a rol. And yes, surprisingly, doing 4x{shift, and, or} takes about twelve times more cycles than a single shift.Again, if you're that desperate, th…
17 years, 9 months ago
Latest Activity
See all in DiscussionsNow, if not fast enough yet, have it:1) pull a whole cacheline from src1 into 4 registers.2) multiply by a …
17 years, 9 months ago
In a memory bound kernel, you shouldn't be concerned by instruction pairing (hint: cachelines). You shouldn't be using msvc if …
17 years, 9 months ago
You've asked for a shift, not a rol. And yes, surprisingly, doing 4x{shift, and, or} takes about twelve times more …
17 years, 9 months ago