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Circuit Design Question

Started by Eric Dec 5, 2001 at 1:26 AM 1 replies 650+ views

Original Post

Dec 5, 2001 at 1:26 AM

Pretend this is a stage in the pipeline of a processor. Data from the 1st register works its way through the combinational logic, where a boolean value is ultimately produced (RESULT). If this signal is 1, then some data is written to the 2nd register. Otherwise the contents of the 2nd register must remain intact. The problem is, at the beginning of the cycle, RESULT still has its old value from the previous cycle. If it is 1, then the write would occur, even if SIGNAL eventually changes to 0 later in the cycle. My proposed solution is the "delay circuit". Assume RESULT_IS_VALID was 0 in the previous cycle. It is changed to 1 at the start of the current cycle, but because of the delay circuit, this 1 does not propogate to the AND gate until after the the new value for RESULT has propogated through the combinational logic. Is this a reasonable, realistic solution? (It seems kludgy.) Also, I have no idea how the delay circuit should be implemented. Lastly, this processor''s clock can apparently be set to different rates, and I don''t know if a fixed delay would work for all clock rates.

GuyJohnston

Dec 5, 2001 at 9:30 AM

It''s been anlong time since I''ve done stuff like this.
You will have to bear with me while I catch up.

I initially thought you could use a JK Flip Flop to feed
result into and control the Flip Flop by feeding the output
back into the Flip Flop clock. That could give you a positive
edge control.

However, I don''t fully understand the problem.

I assume a write occurs when Write Enable is held high,
and doesn''t occur when held low.

I also assume that if Result is held high, you want to enable
a write, if low you want to disable the write.

I don''t understand why routing the Result directly to
Write Enable doesn''t work. Can you clear this up ?

Mayrel

Dec 5, 2001 at 10:04 AM

It looks like you want to make a sort of ''conditional register assignment''. Depending on the value held in the left register (which I''ll call r0), you may want to set the value in the right register (which I''ll call r1).

No immediately obvious use for such a system springs to mind. Perhaps you''ve presented a simplified form of the actual system?

Two things spring to mind. Firstly the combinational logic unit (CLU) won''t be sending a 1 along the result line unless its told to. This means that as long as you give enough time between cycles for any current that''s flowing along result to be taken away, you won''t have a problem with result being high.

Secondly, if you still need a delay, then you''ll need a delay circuit. In my view, your solution isn''t entirely kludgy, but I think it would be better if the delay unit was in the CLU.

That would be quite elegant - each component is responsible for telling components it is connected to when it has finished its task. That way, you can change the CLU and not have to change any of the delay units that might be waiting to do something else that is dependent upon the CLU having completed - because the only delay unit that tells components when the CLU has finished is in the CLU itself.

Just Plain Wrong

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