Rendering 3D Gaussians on a Graph Processor

Researchers have built the first 3D Gaussian renderer for an Intelligence Processing Unit, using 1,472 independent tiles with only on-chip SRAM. Each tile owns a screen-space region, and Gaussian primitives are routed across the chip with Manhattan-distance hops on a north-east-west-south grid before being fanned out to overlapping neighbors. The work is aimed at real-world 3D Gaussian maps from captured sequences, so it’s not just a toy architecture demo.

For graphics programmers, the interesting part is the execution model: the renderer is designed around the IPU’s bulk synchronous parallel approach, with inter-tile communication fixed at compile time. That makes locality the main optimization target. Instead of leaning on large caches or DRAM bandwidth, the implementation tries to keep data moving between nearby tiles and exploit the spatial structure of the splat workload.

The team also digs into the hard limits of an SRAM-only renderer: inter-tile bandwidth, per-tile memory capacity, and load imbalance when Gaussian density is uneven. Those are exactly the kinds of bottlenecks that show up in real engine work when a technique scales from a paper demo to messy content. The quality/performance tradeoff here is especially relevant for anyone evaluating whether a new representation can survive constrained hardware.

The broader takeaway is that this could inform more than just IPUs. The work raises the possibility that direct communication between GPU streaming multiprocessors, or other on-chip producer/consumer paths, could reduce DRAM traffic in future kernels. For...